The present invention relates generally to metal-oxide semiconductor dynamic random-access memories, and more specifically to a one-transistor dynamic memory cell structure.
In a prior art one-transistor dynamic MOS memory, memory cells are defined on a major surface of a p-type silicon substrate 101, as shown in FIG. 1, by separator 102, and n.sup.+ -type regions 106 are formed in the substrate to act as source and drain electrodes of a MOS structure. Insulators 103 are deposited on the substrate and a gate electrode 104 is formed on each insulator 103. A capacitor, which is formed in a first interlayer insulator 108 by a cell electrode 109, a tantalum oxide charge storage layer 111 and a common electrode 110, is located side-by-side with the gate insulator 103, while making an electrical contact with one of the n.sup.+ regions. The other n.sup.+ -type region is coupled to the n.sup.+ -type regions of other memory cells by a bit-line conductor 105 which is formed in the first and second interlayer insulators 108 and 112. On the bit line 105 is a third interlayer insulator 113 on which a wiring layer is formed.
Because of the side-by-side arrangement of the cell capacitors, gate electrodes and the contact portions of the bit line, it is difficult to reduce the horizontal dimensions of the memory without reducing the mechanical strength of the memory to withstand punch-through pressure. Another shortcoming of the prior art lies in the difficulty to provide a sufficient amount of storage capacity for each memory cell partly because an increased vertical dimension of the capacitors makes it difficult to machine contact holes for the bit line and partly because the heat-vulnerable tantalum oxide layers must be subjected to repeated annealing processes.